1. Field of Invention
The present invention is related to a semiconductor device manufacturing method and a semiconductor manufacturing apparatus, and more particularly to a semiconductor device manufacturing method and a semiconductor manufacturing apparatus, which comprise a process for forming an extremely ragged HSG (Hemi-spherical Grained Silicon) on the surface of an amorphous silicon layer, and for making this HSG formed layer (HSG layer) a capacitor electrode having a large surface area.
2. Description of Related Art
A conventional DRAM (Dynamic Random Access Memory) capacitor cell having a capacitor electrode comprising an HSG layer will be explained by referring to FIG. 9. Layer 1 is a silicon substrate, on which are formed a field oxide layer 2, source 3, and drain 4, respectively. Layer 5 is a gate oxide layer formed on the silicon substrate 1 between the source 3 and the drain 4. Layer 6 is a gate electrode formed on the gate oxide layer 5, layer 7 is a silicon interlevel dielectric layer, and element 8 is a contact hole formed in the interlevel dielectric layer 7 above the source 3.
An amorphous silicon layer is deposited on the interlevel dielectric layer 7 extending between the source-drain, patterning is performed, a natural oxide layer of the amorphous silicon layer is removed following cleaning, crystallization is carried out, and a bottom electrode 9 is formed. Next, an Si3N4 capacitor dielectric layer 13 is formed, and a top electrode 11 is formed thereon using a polysilicon layer or the like. A DRAM having a capacitor cell in the source 3 of a MOS (Metal-Oxide Semiconductor) transistor can be realized in this fashion.
Now, a DRAM capacitor is required to have a nearly fixed capacitance value, but because the area occupied by a capacitor cell decreases as the level of DRAM integration increases, the lowering of the capacitor capacitance value cannot be avoided. As methods for maintaining the capacitor capacitance value at a fixed level, the capacitor dielectric layer can be made into a thin film, a dielectric layer with a high dielectric constant can be used, and/or the surface of the electrode can be enlarged, but making the Si3N4 layer used as a capacitor dielectric layer thinner has about reached its limit. Consequently, the use of a high dielectric constant dielectric layer such as a Ta2O5 layer instead of a low dielectric constant dielectric layer like Si3N4 is under study. However, the problem with a high dielectric constant dielectric layer is that the conditions for forming same are troublesome, and even for a Ta2O5 layer, which is an especially promising candidate, post-formation processing is uncertain, and is still in the research stage, and it is not yet ready to be used in volume production. Therefore, until such time as a high dielectric constant dielectric layer can be utilized, the situation is such that maintaining the capacitor capacitance value must be achieved by enlarging the surface area of the electrode.
There are some methods for enlarging the surface of an electrode. One is stacking. Capacitor capacitance is greatly increased by stacking, but because this poses problems for such downscaling techniques as depth-of-focus exposure and dry etching, other methods are being sought. Among these, as shown in FIG. 10, there has been proposed a capacitor electrode portion formation technology (Japanese Patent Laid-open No. 5-304273 (U.S. Pat. No. 2,508,948)), which, in accordance with controlling the nuclei formation temperature of a pre-crystallization amorphous silicon, which constitutes a bottom electrode 9, forms a bumpy HSG 12 on the silicon surface, making the surface area of the formed HSG 12 thereof 2 or more times greater than the surface area of a polysilicon layer formed, for example, at 600° C.
This proposal is premised on the surface of the amorphous silicon layer being in a substantially clean state, and does not particularly limit the thin film formation method to a CVD (Chemical Vapor Deposition) or a MBE (Molecular-Beam Epitaxy) method, and because it enables the size of the crystal grain to be controlled easily by raising the heating temperature for crystal nuclei generation, and lowering the temperature for crystal nuclei growth, it diminishes the size of the average crystal grain in accordance with generating crystal nuclei by heating the amorphous silicon layer at a prescribed temperature, and then growing crystal nuclei by lowering the temperature.
Further, this proposal is constituted so that crystal nuclei generation and growth are carried out at the same temperature, but control of crystal grain density and crystal grain size is facilitated in accordance with shutting off at crystal nuclei growth the supply of a silicon compound gas supplied during crystal nuclei formation, enabling the formation of a polysilicon layer with an even finer grain size.
Furthermore, there is a method, which is described in detail in the above-mentioned announcement, and this method particularly limits the thin film formation method to an MBE method, and by generating crystal nuclei in accordance with irradiating an amorphous silicon layer with a silicon molecular beam while applying heat at a prescribed temperature, and by continuing to apply heat but not irradiating a silicon molecular beam during crystal nuclei growth, enables the generation of crystal nuclei at a low temperature without using a chemical reaction.
Referring to the above-mentioned HSG layer formation, the following items are required:
(1) From the standpoint of semiconductor device yield, uniform HSG grain size and grain density. For this reason, it is necessary to eliminate defects, thus making surface state, as well as temperature control extremely important until an HSG layer is formed. HSG is a technology, which makes use of volumetric fluctuations generated in the process of changing from an amorphous to a polycrystalline state, and what is referred to herein as a defect is a portion, which constitutes a state in which an amorphous silicon substrate is converted to a crystal, volumetric fluctuation is retarded, and HSG is not formed.
(2) The possibility of selective HSG layer growth. Here, selective HSG layer growth refers to the formation, in the process for forming the capacitor electrode portion of FIG. 9, of HSG only on the surface of the amorphous silicon layer-based bottom electrode 9 of the capacitor electrode portion, without forming HSG on the surface of the interlevel dielectric layer 7 of the non-capacitor electrode portion exposed by capacitor electrode isolation, which forms the bottom electrode 9 relative to the interlevel dielectric layer 7 comprising a silicon-based dielectric layer. In the formation of HSG, it is necessary that only the crystal nuclei of a silicon layer (possible at low temperatures over a short period of time) be formed and grown on an amorphous silicon layer, without growing a silicon layer. The reason HSG is not grown on a dielectric layer, such as a silicon-based dielectric layer, is because incubation time until silicon layer nuclei formation is longer than on an amorphous silicon layer. The reason such selective HSG growth is required is because when the non-capacitor electrode portion is covered by a silicon layer in accordance with the formation of HSG, etchback must be performed once again, thereby increasing the number of manufacturing processes of a semiconductor device, and increasing the danger that the capacitor electrode sidewall portion will be etched as a result of etchback.
(3) Relating to HSG formation throughput, it is desirable that it be 16 wafers or more per hour with a batch mode vertical-type apparatus.
From the standpoint thereof, with a constitution that uses the MBE method in the above-mentioned announcement, the uniformity of HSG grain size and grain density of the above-described (1) is good, but the selective growth of (2) is not possible, and it is difficult to achieve the throughput of (3).
Conversely, the use of a CVD method in the formation of capacitor electrode portion HSG is also explained in the above-mentioned announcement. With a CVD method, temperature control becomes especially important, but a specific example thereof is not provided in the above-mentioned announcement. Accordingly, an HSG formation technology that utilizes a CVD method is discussed hereinbelow. A layer formation method using a CVD apparatus constitutes a batch mode and a single wafer mode.
In the batch mode, a batch mode vertical-type apparatus is ordinarily utilized. With this apparatus, because heating of a wafer is from the side surface due to the fact that it is peripheral heating, which applies heat from an external portion of a reaction tube, inplane temperature uniformity is difficult to achieve. Further, a time difference occurs from the entry into the furnace of the top portion of a wafer boat, in which a plurality of wafers are mounted, until the entry into the furnace of the bottom portion of the wafer boat, and a time difference occurs between the egress from the furnace of the bottom portion, and the egress from the furnace of the top portion of a wafer boat. Consequently, due to the fact that the heat history differs between a wafer located at the top of a boat, and a wafer located at the bottom of a boat, the inplane/inter-surface heat distribution of the wafers is susceptible to variation. Therefore, the problem is that because the surface condition of a wafer on which a layer is to be formed, as well as the nuclei formation temperature are not fixed, a prescribed grain density cannot be uniformly achieved in an HSG, and HSG grain size is not uniform.
Temperature stability is necessary to form HSG grain size and grain density uniformly, but in the batch mode, the formation period to achieve a prescribed HSG grain size and grain density requires a long time. However, the continuous heating of a wafer over a long period of time makes defects more apt to occur. That is, the problem is that the base amorphous silicon layer is crystallized, thereby making HSG formation more prone to retardation. This problem can theoretically be solved by optimizing temperature and time, but in actuality, the optimization of process conditions is impossible. Further, when HSG formation takes a long time, throughput is lowered. Therefore, all the conditions of the above-mentioned (1)-(3) cannot be satisfied even using the technology of the above-mentioned announcement in the batch mode.
Meanwhile, in the single wafer mode, there is a constitution that uses a cold-wall-type single wafer mode apparatus, and a constitution that uses a hot-wall-type single wafer mode apparatus.
With a cold-wall-type single wafer mode apparatus, in which a wafer is heated by a heater mounted inside a reaction chamber, due to the fact that a temperature difference of around ±1.0° C. between the center portion and the peripheral portion of a wafer, wafer inplane uniformity is apt to deteriorate during HSG grain formation. Therefore, even if the technology of the above-mentioned announcement were to be used in a cold-wall-type single wafer apparatus, the conditions of at the least (1) could not be satisfied.
By contrast thereto, with a hot-wall-type single wafer mode apparatus, in which a wafer is heated using a heater or the like from the outer surface of a reaction chamber, because of good partitioned heater control, both wafer inter-surface and inplane temperatures can be made uniform in accordance with performing partitioned heater control, but the optimum conditions for HSG formation are unclear. Furthermore, it is said that even if partitioned heater control is performed in a cold-wall system, inplane temperature uniformity is not as good as it is with a hot-wall system.
As described above, with a batch mode, the problem is process related in that a long time is required until temperatures stabilize, and with a cold-wall system, because of the difficulty maintaining temperature uniformity, HSG uniformity is prone to deterioration. By contrast thereto, a single wafer mode hot-wall system is effective, but the optimum conditions for HSG uniformity are unclear.
An object of the present invention is to provide, in the HSG process, wherein temperature control becomes the key point, a semiconductor device manufacturing method, which solves for the above-mentioned problem points of conventional technologies by finding the optimum conditions of the HSG process, and which is capable of forming a stable HSG layer with no defects, and further, which makes it possible to furnish selectivity.
Further, an object of the present invention is to provide a semiconductor manufacturing apparatus, which is capable of implementing the above-mentioned manufacturing method in accordance with slight changes to existing equipment.